1. Technical Field
The present teaching relates to method and system for analog circuits. More specifically, the present teaching relates to method and system for limiting amplifiers and systems incorporating the same.
2. Discussion of Technical Background
Modern high-performance communication systems increasingly rely on precision clocks for data conversion. Clocks used to drive analog-to-digital converters (ADC's) sample the analog input signal, where any imperfections in the sampling timing will result in imperfections in the output data. Such imperfections can be characterized by degradation of the ADC signal-to-noise ratio (SNR), where it is known that the SNR degradation due to clock imperfections is proportional to both clock jitter and the analog input frequency. It is commonly known that this SNR degradation is indistinguishable from SNR degradation caused by quantization noise or other noise present on the analog input signal.
As digital processing capability continues to improve, it has become popular to digitize signals earlier and earlier in the signal chain, hence at ever higher frequencies. For example, both direct-IF and even direct-RF receivers have become common. In these applications, an ADC is actually under-sampled. Under-sampling takes advantage of the fact that as long as the sampling occurs at the Nyquist frequency of the bandwidth of interest or above, the modulated signal can be recovered. Therefore, an analog input signal can actually be sampled at a frequency much lower than its carrier frequency, and the sampled data still retains the modulated content of interest.
However, under-sampling places stringent requirements on the clock used for the sampling. As noted above, the SNR degradation due to jitter is dependent on both clock jitter and analog input frequency. In an under-sampled ADC, the clock will still be sampling a signal with the high slew-rates of the analog carrier input. So, as the analog input frequency increases, often a significant limitation to the SNR performance is clock jitter.
Both clock jitter and phase noise are measures of clock variation. Phase noise is defined as the power spectral density of the phase variation of a signal. Thus, it is a frequency domain quantity. Integration of the phase noise over a specified offset frequency bandwidth converts it to a time-domain quantity, or aperture jitter, which is considered to be the variations of the clock zero-crossings relative to the zero-crossings of an ideal clock. Although there are other jitter metrics that reflect period variations and adjacent cycle variations of a clock, the most descriptive measure of clock variation is phase noise, because no offset frequency specific information is lost.
A complication in designing low phase noise clocking systems is the issue of frequency aliasing. In sampled data systems such as ADC's, aliasing of the clock spectrum will occur for frequency content beyond the sampling frequency. As noted by W. Egan in the paper “Modeling Phase Noise in Frequency Dividers,” IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control, Volume 37, Issue 4, July 1990, pages 310-311, a similar issue occurs for frequency dividers used in synthesizer applications. In both situations, large bandwidths in a clock path can result in degraded phase noise due to noise folding into the baseband. For this reason, as is noted in the U.S. Pat. No. 7,345,528, “Method and Apparatus for Improved Clock Preamplifier with Low Jitter”, columns 2-3, it is a common practice to design high performance communications systems with a bandpass filter following a low-noise sine-wave signal. Such a bandpass filter aims at reducing the out of band noise to minimize degradation in overall phase noise caused by spectral folding.
In most situations, the output of such a bandpass filter is followed by a limiting amplifier to “square up” the signal before it is used to sample data (in ADC applications) or clock a frequency divider (in frequency synthesizer applications). The “squaring-up” of the clock is done to minimize the region where sampler or divider noise adversely affects the output signal noise. As noted by C. Xu, et al. in “Analysis of Clock Buffer Phase Noise”, 9th International Conference on Electronics, Circuits and Systems, 2002, Volume 2, September 2002, pages 425-428, the output phase noise scaling factor for a clock amplifier is improved by ensuring fast, symmetrical rising and falling output signals. A similar observation can be made that conversion of voltage noise to timing jitter is proportional to the inverse of slew-rate. Therefore, having a high slew-rate clock signal is highly desirable.
It is often assumed that the output slew rate of an amplifier stage is determined by the charging of parasitic capacitors. While this is the case for a limiting amplifier driven by a high slew-rate signal, it is not the case when the limiting amplifier is driven by a slow sine wave or other low slew-rate input. Thus, it is a challenge for a limiting amplifier to achieve low phase noise when it is presented with a low slew-rate input, especially because a limiting amplifier is usually designed to operate over a wide range of input slew-rates.
A typical limiting amplifier includes a series of cascaded gain stages 120, 130, . . . , 140, 150 that take an input signal 110 and produce an output signal 160, as shown in FIG. 1 (Prior Art), which not only limit the signal amplitude, but also increase the output slew rate. A common configuration for a gain stage of a prior art limiting amplifier is a circuit 200 shown in FIG. 2 (Prior Art). In this circuit 200, there is a differential pair Q0 215 and Q1 225 as well as corresponding emitter followers 240 and 235, respectively. In such an implementation, bipolar devices are chosen based on their superior 1/f noise characteristics. However, large MOSFET devices may also be used. When a differential signal applied to the base inputs of the differential pair circuit, or nodes 205 IN+ and 210 IN−, has a high slew-rate, the output slew-rate is limited by the charging of parasitic capacitances, such as ITAIL charging parasitic capacitors at the outputs of the differential pair circuit, or nodes 225 DP+ and 215 DP−.
In this configuration, any increase in parasitic capacitance at critical nodes, e.g., nodes 225 DP+ and 215 DP−, will degrade the output slew rate. But in case of a low slew-rate input signal, the parasitic capacitances play less of a role in output slew-rate, which is primarily determined by the amplifier gain multiplied by the input slew-rate.
An important observation is that any circuit bandwidth beyond that which improves or maintains the output slew-rate will degrade the output phase noise because of the increasing effect of noise folding, as described earlier. Given such observations, it is desirable to limit the bandwidth when a low slew-rate input is applied to reduce the degradation in phase noise caused by excess bandwidth. This may be achieved by adding a filter to a limiting amplifier stage so that broadband noise can be reduced and output phase noise can be improved without affecting the output slew-rate. In fact, an optimal bandwidth reduction may actually result in a slight reduction of output slew rate. This is because, up to a point determined by circuit characteristics and operating conditions, the output noise reduction may outweigh the slew-rate reduction and actually result in superior phase noise.
U.S. Pat. No. 4,591,805, describes a method of implementing an adaptive bandwidth amplifier. An example adaptive bandwidth amplifier gain stage 300 is illustrated in FIG. 3 (Prior Art). Similar to the circuit shown in FIG. 2, circuit 300 includes a pair of differential bipolar transistors Q0 320 and Q1 330. The differential bipolar transistors receive differential input IN+ 305 and IN− 310 and produce, via their followers output OUT+ 370 and OUT− 375. Otherwise, in circuit 300, a capacitor 315 is introduced across the base-collector nodes of the bipolar transistor Q0 320 and another capacitor 325 is introduced across the base-collector nodes of the bipolar transistor Q1 330. With this construction, circuit 300 takes advantage of the Miller multiplication property, which results in an increased effective capacitance proportional to the gain. In addition to allowing small capacitors 315 and 325 (or CCB) to achieve a specific bandwidth reduction, this prior art circuit 300 also allows adaptive bandwidth control as the input signal swing varies due to the gain dependence of the effective input capacitance.
One drawback of circuit 300 for filtering broadband noise is that, in addition to creating a dominant pole, this configuration also results in a zero at gm/CCB. Because of this zero, as frequency increases, the gain flattens until other poles take effect. Therefore, a single-pole filter at the same frequency as a dominant pole of circuit 300 is actually more effective for filtering broadband noise. Another observation is that inputs IN+ 305 and IN− 310 connecting to the bases of transistors Q0 320 and Q1 330, as shown in FIG. 3, likely are driven by a low impedance source, particularly in the context of a limiting amplifier as described earlier. In this case, the Miller multiplied effective capacitance at the base nodes of Q0 320 and Q1 330 likely will have less effect on circuit bandwidth than the effective capacitance at the collectors of Q0 320 and Q1 330, since the collector nodes will usually be higher impedance. Therefore, an improved approach for effective reduction of bandwidth is needed.